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<title>Memory controller</title>

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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Memory controller</span></span>

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<p>A <b>memory controller</b>, also known as <b>memory chip controller</b> (<b>MCC</b>) or a <b>memory controller unit</b> (<b>MCU</b>), is a digital circuit that manages the flow of data going to and from a computer's <a href="Main_memory" class="mw-redirect" title="Main memory">main memory</a>.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> When a memory controller is integrated into another chip, such as an integral part of a <a href="Microprocessor" title="Microprocessor">microprocessor</a>, it is usually called an <b>integrated memory controller</b> (<b>IMC</b>).

</p><p>Memory controllers contain the logic necessary to read and write to <a href="Dynamic_random-access_memory" title="Dynamic random-access memory">dynamic random-access memory</a> (DRAM), and to provide the critical <a href="Memory_refresh" title="Memory refresh">memory refresh</a> and other functions. Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the <a href="Multiplexer" title="Multiplexer">multiplexer</a> circuit, where the <a href="Demultiplexer" class="mw-redirect" title="Demultiplexer">demultiplexer</a> on the DRAM uses the converted inputs to select the correct memory location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required <a href="Bus_(computing)" title="Bus (computing)">bus</a> width for the operation. Memory controllers' bus widths range from <a href="8-bit" class="mw-redirect" title="8-bit">8-bit</a> in earlier systems, to 512-bit in more complicated systems, where they are typically implemented as four <a href="64-bit" class="mw-redirect" title="64-bit">64-bit</a> simultaneous memory controllers operating in parallel, though some operate with two 64-bit memory controllers being used to access a <a href="128-bit" class="mw-redirect" title="128-bit">128-bit</a> memory device.

</p><p>Some memory controllers, such as the one integrated into <a href="PowerQUICC" title="PowerQUICC">PowerQUICC</a> II processors, include <a href="Error_detection_and_correction" title="Error detection and correction">error detection and correction</a> hardware.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> Many modern processors are also integrated <a href="Memory_management_unit" title="Memory management unit">memory management unit</a> (MMU), which in many <a href="Operating_system" title="Operating system">operating systems</a> implements <a href="Virtual_addressing" class="mw-redirect" title="Virtual addressing">virtual addressing</a>. On early x86-32 processors, the MMU is integrated in the CPU, but the memory controller is usually part of <a href="Northbridge_(computing)" title="Northbridge (computing)">northbridge</a>.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>

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<div class="mw-heading mw-heading2"><h2 id="History">History</h2></div>

<p>Older Intel and <a href="PowerPC" title="PowerPC">PowerPC</a>-based computers have memory controller chips that are separate from the main processor. Often these are integrated into the <a href="Northbridge_(computing)" title="Northbridge (computing)">northbridge</a> of the computer, also sometimes called a memory controller hub.

</p><p>Most modern desktop or workstation microprocessors use an <b>integrated memory controller</b> (<b>IMC</b>), including microprocessors from <a href="Intel" title="Intel">Intel</a>, <a href="AMD" title="AMD">AMD</a>, and those built around the <a href="ARM_architecture" class="mw-redirect" title="ARM architecture">ARM architecture</a>. Prior to <a href="AMD_K8" title="AMD K8">K8</a> (circa 2003), <a href="AMD" title="AMD">AMD</a> microprocessors had a memory controller implemented on their motherboard's <a href="Northbridge_(computing)" title="Northbridge (computing)">northbridge</a>. In K8 and later, AMD employed an integrated memory controller.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> Likewise, until <a href="Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> (circa 2008), <a href="Intel" title="Intel">Intel</a> microprocessors used memory controllers implemented on the motherboard's northbridge. Nehalem and later switched to an integrated memory controller.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> Other examples of microprocessor architectures that use <i>integrated memory controllers</i> include <a href="NVIDIA" class="mw-redirect" title="NVIDIA">NVIDIA</a>'s <a href="Fermi_(microarchitecture)" title="Fermi (microarchitecture)">Fermi</a>, <a href="IBM" title="IBM">IBM</a>'s <a href="POWER5" title="POWER5">POWER5</a>, and <a href="Sun_Microsystems" title="Sun Microsystems">Sun Microsystems</a>'s <a href="UltraSPARC_T1" title="UltraSPARC T1">UltraSPARC T1</a>.

</p><p>While an integrated memory controller has the potential to increase the system's performance, such as by reducing <a href="Memory_latency" title="Memory latency">memory latency</a>, it locks the microprocessor to a specific type (or types) of memory, forcing a redesign in order to support newer memory technologies. When <a href="DDR2_SDRAM" title="DDR2 SDRAM">DDR2 SDRAM</a> was introduced, AMD released new <a href="Athlon_64" title="Athlon 64">Athlon 64</a> CPUs. These new models, with a DDR2 controller, use a different physical socket (known as <a href="Socket_AM2" title="Socket AM2">Socket AM2</a>), so that they will only fit in motherboards designed for the new type of RAM. When the memory controller is not on-die, the same CPU may be installed on a new motherboard, with an updated northbridge to use newer memory.

</p><p>Some microprocessors in the 1990s, such as the DEC <a href="Alpha_21066" class="mw-redirect" title="Alpha 21066">Alpha 21066</a> and HP <a href="PA-7300LC" class="mw-redirect" title="PA-7300LC">PA-7300LC</a>, had integrated memory controllers; however, rather than for performance gains, this was implemented to reduce the cost of systems by eliminating the need for an external memory controller.

</p><p>Some CPUs are designed to have their memory controllers as dedicated external components that are not part of the chipset. An example is IBM <a href="POWER8" title="POWER8">POWER8</a>, which uses external <a href="Centaur_(computing)" class="mw-redirect" title="Centaur (computing)">Centaur</a> chips that are mounted onto <a href="DIMM" title="DIMM">DIMM</a> modules and act as memory buffers, <a href="L4_cache" class="mw-redirect" title="L4 cache">L4 cache</a> chips, and as the actual memory controllers. The first version of the Centaur chip used DDR3 memory but an updated version was later released which can use DDR4.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup>

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<div class="mw-heading mw-heading2"><h2 id="Security">Security</h2></div>

<p>A few experimental memory controllers contain a second level of address translation, in addition to the first level of address translation performed by the CPU's <a href="Memory_management_unit" title="Memory management unit">memory management unit</a> to improve cache and bus performance.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup>

</p><p>Memory controllers integrated into certain <a href="Intel_Core" title="Intel Core">Intel Core</a> processors provide <b>memory scrambling</b> as a feature that turns user data written to the main memory into <a href="Pseudo-random" class="mw-redirect" title="Pseudo-random">pseudo-random</a> patterns.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> Memory scrambling has the potential to prevent <a href="Computer_forensics" title="Computer forensics">forensic</a> and <a href="Reverse-engineering" class="mw-redirect" title="Reverse-engineering">reverse-engineering</a> analysis based on <a href="DRAM_data_remanence" class="mw-redirect" title="DRAM data remanence">DRAM data remanence</a> by effectively rendering various types of <a href="Cold_boot_attack" title="Cold boot attack">cold boot attacks</a> ineffective. In current practice, this has not been achieved; memory scrambling has only been designed to address DRAM-related electrical problems. The late 2010s memory scrambling standards do address security issues and are not cryptographically secure or open to public revision or analysis.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup>

</p><p>ASUS and Intel have their separate memory scrambling standards. ASUS motherboards have allowed the user to choose which memory scrambling standard to use (ASUS or Intel) or whether to turn the feature off entirely.

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<div class="mw-heading mw-heading2"><h2 id="Variants">Variants</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Double_data_rate_memory">Double data rate memory</h3></div>

<p><a href="Double_data_rate" title="Double data rate">Double data rate</a> (DDR) memory controllers are used to drive <a href="DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a>, where data is transferred on both rising and falling edges of the system's memory clock. DDR memory controllers are significantly more complicated when compared to single data rate controllers, but they allow for twice the data to be transferred without increasing the memory's clock rate or bus width.

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<div class="mw-heading mw-heading3"><h3 id="Multichannel_memory">Multichannel memory</h3></div>

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</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Multi-channel_memory_architecture" title="Multi-channel memory architecture">Multi-channel memory architecture</a></div>

<p>Multichannel memory controllers are memory controllers where the DRAM devices are separated onto multiple buses to allow the memory controller(s) to access them in parallel. This increases the theoretical amount of bandwidth of the bus by a factor of the number of channels. While a channel for every DRAM would be the ideal solution, adding more channels increases complexity and cost.

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<div class="mw-heading mw-heading3"><h3 id="Fully_buffered_memory">Fully buffered memory</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Fully_Buffered_DIMM" title="Fully Buffered DIMM">Fully Buffered DIMM</a></div>

<p>Fully buffered memory systems place a memory buffer device on every <a href="DIMM" title="DIMM">memory module</a> (called an <a href="FB-DIMM" class="mw-redirect" title="FB-DIMM">FB-DIMM</a> when fully buffered RAM is used), which unlike traditional memory controller devices, use a serial data link to the memory controller instead of the parallel link used in previous RAM designs. This decreases the number of wires necessary to place the memory devices on a motherboard (allowing for a smaller number of layers to be used, meaning more memory devices can be placed on a single board), at the expense of increasing latency (the time necessary to access a memory location). This increase is due to the time required to convert the parallel information read from the DRAM cell to the serial format used by the FB-DIMM controller, and back to a parallel form in the memory controller on the motherboard.

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<div class="mw-heading mw-heading3"><h3 id="Flash_memory_controller">Flash memory controller</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Flash_memory_controller" title="Flash memory controller">Flash memory controller</a></div>

<p>Many <a href="Flash_memory" title="Flash memory">flash memory</a> devices, such as <a href="USB_flash_drive" title="USB flash drive">USB flash drives</a> and <a href="Solid-state_drive" title="Solid-state drive">solid-state drives</a>, include a <a href="Flash_memory_controller" title="Flash memory controller">flash memory controller</a>. Flash memory is inherently slower to access than RAM and often becomes unusable after a few million write cycles, which generally makes it unsuitable for RAM applications.

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<ul><li><a href="Address_generation_unit" title="Address generation unit">Address generation unit</a></li>

<li><a href="Memory_scrubbing" title="Memory scrubbing">Memory scrubbing</a></li>

<li><a href="Storage_controller" title="Storage controller">Storage controller</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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<li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text">Comptia A+ Certification Exam Guide, Seventh Edition, by Mike Meyers, in the glossary, bottom of page 1278: "Chip that handles memory requests from the CPU."</span>

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</style><cite id="CITEREFNeat2003" class="citation book cs1">Neat, Adam G. (2003-12-04). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=PJ49xcoRb1QC&q=%22memory+controller+unit%22&pg=PA100"><i>Maximizing Performance and Scalability with IBM WebSphere</i></a>. Apress. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>9781590591307</bdi><span class="reference-accessdate">. Retrieved <span class="nowrap">6 February</span> 2015</span>.</cite></span>

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<li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.freescale.com/files/training_pdf/24815_PQ2_MEM_CONTROL_WBT.pdf">"Memory Controller"</a></span>

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<li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external free" href="https://vikramuniv.ac.in/files/academic/e-Resources2020-21/engg2020-21/BE_6_SEM_EE_MP_MC-_COMP._OF_8086_FAMILY-AMIT_THAKUR-converted-converted.pdf">https://vikramuniv.ac.in/files/academic/e-Resources2020-21/engg2020-21/BE_6_SEM_EE_MP_MC-_COMP._OF_8086_FAMILY-AMIT_THAKUR-converted-converted.pdf</a></span>

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<li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><cite id="CITEREFVries" class="citation web cs1">Vries, Hans de. <a rel="nofollow" class="external text" href="http://www.chip-architect.com/news/2001_10_02_Hammer_microarchitecture.html">"Chip Architect: AMD's Next Generation Micro Processor's Architecture"</a>. <i>www.chip-architect.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2018-03-17</span></span>.</cite></span>

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</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110929024052/http://www.kingston.com/newtech/MKF_520DDRwhitepaper.pdf">Infineon/Kingston (a memory vendor) Dual Channel DDR Memory Whitepaper</a> at the <a href="Wayback_Machine" title="Wayback Machine">Wayback Machine</a> (archived 2011-09-29) – explains dual channel memory controllers, and how to use them</li>

<li><a rel="nofollow" class="external text" href="https://www.utmel.com/blog/categories/memory%20chip/what-is-a-memory-controller/">Introduction to Memory Controller</a></li>

<li><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/support/articles/000005657/boards-and-kits.html">Intel guide on Single- and Multichannel Memory Modes</a></li>

<li><a rel="nofollow" class="external text" href="https://www.embedic.com/technology/details/what-is-a-memory-controller">What is a Memory Controller and How Does it Work</a></li>

<li><a rel="nofollow" class="external text" href="https://www.jotrin.com/technology/details/what-is-memory-controller">What is Memory Controller?</a></li>

<li><a rel="nofollow" class="external text" href="https://www.lisleapex.com/blog-memory-controllers-history-and-how-it-work">Memory Controllers:History and How it Work</a> [<i><a href="Sic" title="Sic">sic</a></i>]</li>

<li><a rel="nofollow" class="external text" href="https://www.dyethin.com/blog/industry/what-is-a-flash-memory-everything-you-need-to-know!">Flash Memory: Types and Development History</a></li></ul>

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</style><div id="Processor_technologies439" style="font-size:114%;margin:0 4em"><a href="Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Abstract_machine" title="Abstract machine">Abstract machine</a></li>

<li><a href="Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li>

<li><a href="Finite-state_machine" title="Finite-state machine">Finite-state machine</a>

<ul><li><a href="Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li>

<li><a href="Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li>

<li><a href="Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li>

<li><a href="Queue_automaton" title="Queue automaton">Queue automaton</a></li>

<li><a href="Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li>

<li><a href="Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li>

<li><a href="Turing_machine" title="Turing machine">Turing machine</a>

<ul><li><a href="Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li>

<li><a href="Universal_Turing_machine" title="Universal Turing machine">Universal</a></li>

<li><a href="Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li>

<li><a href="Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li>

<li><a href="Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li>

<li><a href="Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li>

<li><a href="Hypercomputation" title="Hypercomputation">Hypercomputation</a></li>

<li><a href="Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li>

<li><a href="History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li>

<li><a href="Stack_machine" title="Stack machine">Stack machine</a></li>

<li><a href="Register_machine" title="Register machine">Register machines</a>

<ul><li><a href="Counter_machine" title="Counter machine">Counter</a></li>

<li><a href="Pointer_machine" title="Pointer machine">Pointer</a></li>

<li><a href="Random-access_machine" title="Random-access machine">Random-access</a></li>

<li><a href="Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Microarchitecture" title="Microarchitecture">Microarchitecture</a></li>

<li><a href="Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li>

<li><a href="Harvard_architecture" title="Harvard architecture">Harvard</a>

<ul><li><a href="Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li>

<li><a href="Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li>

<li><a href="Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li>

<li><a href="Cellular_architecture" title="Cellular architecture">Cellular</a></li>

<li><a href="Endianness" title="Endianness">Endianness</a></li>

<li><a href="Computer_data_storage" title="Computer data storage">Memory access</a>

<li><a href="Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li>

<li><a href="Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li>

<li><a href="Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li>

<li><a href="Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a>

<ul><li><a href="Virtual_memory" title="Virtual memory">Virtual memory</a></li>

<li><a href="Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li>

<li><a href="Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li>

<li><a href="Fabric_computing" title="Fabric computing">Fabric</a></li>

<li><a href="Multiprocessing" title="Multiprocessing">Multiprocessing</a></li>

<li><a href="Cognitive_computing" title="Cognitive computing">Cognitive</a></li>

<li><a href="Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set<br>architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li>

<li><a href="Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li>

<ul><li><a href="TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li>

<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>

<li><a href="Quantum_computing" title="Quantum computing">Quantum computing</a></li>

<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a>

<ul><li><a href="Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction<br>sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li>

<li><a href="Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li>

<li>Power

<ul><li><a href="IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li>

<li><a href="PowerPC" title="PowerPC">PowerPC</a></li>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a></li></ul></li>

<li><a href="Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li>

<li><a href="SPARC" title="SPARC">SPARC</a></li>

<li><a href="SuperH" title="SuperH">SuperH</a></li>

<li><a href="DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li>

<li><a href="ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li>

<li><a href="Unicore" title="Unicore">Unicore</a></li>

<li><a href="IA-64" title="IA-64">Itanium</a></li>

<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a></li>

<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>

<li>System/3x0

<li><a href="Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li>

<li>Tilera ISA</li>

<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>

<li><a href="Adapteva" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li>

<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li>

<li><a href="Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li>

<li><a href="Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Data_dependency" title="Data dependency">Data dependency</a></li>

<li><a href="Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li>

<li><a href="Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li>

<li><a href="False_sharing" title="False sharing">False sharing</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Scoreboarding" title="Scoreboarding">Scoreboarding</a></li>

<li><a href="Tomasulo's_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a>

<ul><li><a href="Reservation_station" title="Reservation station">Reservation station</a></li>

<li><a href="Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li>

<li><a href="Register_renaming" title="Register renaming">Register renaming</a></li>

<li><a href="Wide-issue" title="Wide-issue">Wide-issue</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Branch_predictor" title="Branch predictor">Branch prediction</a></li>

<li><a href="Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li>

<li><a href="Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li>

<li><a href="Instruction_pipelining" title="Instruction pipelining">Pipelining</a>

<ul><li><a href="Scalar_processor" title="Scalar processor">Scalar</a></li>

<li><a href="Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li>

<ul><li><a href="Thread_(computing)" title="Thread (computing)">Thread</a></li>

<li><a href="Process_(computing)" title="Process (computing)">Process</a></li></ul></li>

<ul><li><a href="Vector_processor" title="Vector processor">Vector</a></li></ul></li>

<li><a href="Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li>

<li><a href="Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Temporal_multithreading" title="Temporal multithreading">Temporal</a></li>

<li><a href="Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a>

<ul><li><a href="Hyper-threading" title="Hyper-threading">Hyperthreading</a></li>

<li><a href="Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li>

<li><a href="Speculative_multithreading" title="Speculative multithreading">Speculative</a></li>

<li><a href="Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li>

<li><a href="Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Flynn's_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Single_instruction%2C_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li>

<li><a href="Flynn's_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li>

<li><a href="Flynn's_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_performance" title="Computer performance">Processor<br>performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Transistor_count" title="Transistor count">Transistor count</a></li>

<li><a href="Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC)

<ul><li><a href="Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li>

<li><a href="Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li>

<li><a href="FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li>

<li><a href="Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li>

<li><a href="SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li>

<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li>

<li><a href="Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li>

<li><a href="Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li>

<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)

<ul><li><a href="General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li>

<li><a href="Vector_processor" title="Vector processor">Vector</a></li>

<li><a href="Barrel_processor" title="Barrel processor">Barrel</a></li>

<li><a href="Stream_processing" title="Stream processing">Stream</a></li>

<li><a href="Tile_processor" title="Tile processor">Tile processor</a></li>

<li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>

<li><a href="Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li>

<li><a href="System_in_a_package" title="System in a package">System in a package</a> (SiP)</li>

<li><a href="Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul>

</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Embedded_system" title="Embedded system">Embedded system</a></li>

<li><a href="Microprocessor" title="Microprocessor">Microprocessor</a></li>

<li><a href="Microcontroller" title="Microcontroller">Microcontroller</a></li>

<li><a href="Mobile_processor" title="Mobile processor">Mobile</a></li>

<li><a href="Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li>

<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems<br>on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li>

<li><a href="Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li>

<li><a href="Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li>

<li><a href="Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_acceleration" title="Hardware acceleration">Hardware<br>accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>

<li><a href="AI_accelerator" class="mw-redirect" title="AI accelerator">AI accelerator</a></li>

<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li>

<li><a href="Image_processor" title="Image processor">Image processor</a></li>

<li><a href="Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li>

<li><a href="Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li>

<li><a href="Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li>

<li><a href="Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li>

<li><a href="Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li>

<li><a href="Network_processor" title="Network processor">Network processor</a></li>

<li><a href="Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul>

</div></td></tr></tbody></table><div>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Bit_slicing" title="Bit slicing">bit slicing</a></li>

<li><a href="Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a>

<ul><li><a href="Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Single-core" title="Single-core">Single-core</a></li>

<li><a href="Multi-core_processor" title="Multi-core processor">Multi-core</a></li>

<li><a href="Manycore_processor" title="Manycore processor">Manycore</a></li>

<li><a href="Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Cache_(computing)" title="Cache (computing)">Cache</a>

<ul><li><a href="CPU_cache" title="CPU cache">CPU cache</a></li>

<li><a href="Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li>

<li><a href="Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li>

<li><a href="Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li>

<li><a href="Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li>

<li><a href="Cache_coherence" title="Cache coherence">coherence</a></li></ul></li>

<li><a href="Clock_rate" title="Clock rate">Clock rate</a></li>

<li><a href="Clock_signal" title="Clock signal">Clock signal</a></li>

</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Execution_unit" title="Execution unit">Functional<br>units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li>

<li><a href="Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li>

<li><a href="Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li>

<li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU)

<ul><li><a href="Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li>

<li><a href="Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li>

<li><a href="Branch_predictor" title="Branch predictor">Branch predictor</a></li>

<li><a href="Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li>

<li> (IMC)

<ul><li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li>

<li><a href="Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Combinational_logic" title="Combinational logic">Combinational</a></li>

<li><a href="Sequential_logic" title="Sequential logic">Sequential</a></li>

<li><a href="Logic_gate" title="Logic gate">Logic gate</a>

<ul><li><a href="Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li>

<li><a href="Gate_array" title="Gate array">Array</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Processor_register" title="Processor register">Processor register</a></li>

<li><a href="Status_register" title="Status register">Status register</a></li>

<li><a href="Stack_register" title="Stack register">Stack register</a></li>

<li><a href="Register_file" title="Register file">Register file</a></li>

<li><a href="Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li>

<li><a href="Memory_address_register" title="Memory address register">Memory address register</a></li>

<li><a href="Program_counter" title="Program counter">Program counter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li>

<li><a href="Instruction_unit" title="Instruction unit">Instruction unit</a></li>

<li><a href="Data_buffer" title="Data buffer">Data buffer</a></li>

<li><a href="Write_buffer" title="Write buffer">Write buffer</a></li>

<li><a href="Microcode" title="Microcode">Microcode</a> <a href="ROM_image" title="ROM image">ROM</a></li>

<li><a href="Counter_(digital)" title="Counter (digital)">Counter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Multiplexer" title="Multiplexer">Multiplexer</a></li>

<li><a href="Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li>

<li><a href="Adder_(electronics)" title="Adder (electronics)">Adder</a></li>

<li><a href="Binary_multiplier" title="Binary multiplier">Multiplier</a>

<li><a href="Binary_decoder" title="Binary decoder">Binary decoder</a>

<ul><li><a href="Address_decoder" title="Address decoder">Address decoder</a></li>

<li><a href="Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li>

<li><a href="Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Integrated_circuit" title="Integrated circuit">Integrated circuit</a>

<li><a href="Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li>

<li><a href="Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li>

<li><a href="Boolean_circuit" title="Boolean circuit">Boolean</a></li>

<li><a href="Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li>

<li><a href="Analogue_electronics" title="Analogue electronics">Analog</a></li>

<li><a href="Quantum_circuit" title="Quantum circuit">Quantum</a></li>

<li><a href="Switch#Electronic_switches" title="Switch">Switch</a></li></ul>

</div></td></tr></tbody></table><div>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Power_management" title="Power management">Power<br>management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li>

<li><a href="Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li>

<li><a href="Clock_gating" title="Clock gating">Clock gating</a></li>

<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li>

<li><a href="Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li>

<li><a href="Processor_design" title="Processor design">Processor design</a></li>

<li><a href="Digital_electronics" title="Digital electronics">Digital electronics</a></li>

<li><a href="Hardware_security_module" title="Hardware security module">Hardware security module</a></li>

<li><a href="Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li>

<li><a href="Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li>

<li><a href="Pin_grid_array" title="Pin grid array">Pin grid array</a></li>

<li><a href="Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul>

</div></td></tr></tbody></table></div></div><div><div class="zim-footer">

This article is issued from <a class="external text" title="Last edited on 2025-07-12" href="https://en.wikipedia.org/wiki/?title=Memory_controller&oldid=1300133995">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

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